The present invention relates generally to integrated circuit memory devices and, more particularly, to a system and method for implementing row redundancy with reduced access time and reduced device area.
Memory devices are commonly employed as internal storage areas in a computer or other type of electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), for example. RAM is typically used as main memory in a computer environment. RAM is generally volatile, in that once power is turned off, all data stored in the RAM is lost.
As is the case with other types of integrated circuit devices, defects can occur during the manufacture of a memory array having rows and columns of individual memory cells. Typical defects can include, for example, bad memory cells, open circuits, shorts between a pair of rows and shorts between a row and column. In any case, defects can reduce the overall yield of the memory device manufacturing process. One way to address this problem, without discarding the memory device, is to incorporate redundant elements in the memory that selectively replace defective elements. For example, redundant rows are one type of redundant element that may be provided in memory to replace a defective primary row.
After a memory die has been manufactured, it is tested for defects. Generally with volatile memory, redundancy circuitry is used to selectively redirect access (address) requests from to the defective elements to the redundant elements. Redundancy circuitry may include, for example, electrical fuses that are selectively “blown” (open circuited) to electrically disconnect the defective rows. The redundant rows are then activated to replace the shorted rows. In addition, some memory devices may utilize non-volatile registers or fuse blocks to permanently store addresses of primary elements that are designated for replacement. The fuse blocks are typically coupled with redundancy control logic that compares address requests to addresses stored in the fuse blocks. If an address request matches an address stored in a fuse block, the redundant circuit directs or maps the access request to the redundant row instead of the defective row in the default or main array.
However, with respect to conventional approaches to row redundancy circuitry, there is typically a design tradeoff between the device real estate occupied by the circuitry and the access/setup time for implementing both the redundancy compare and memory access operations and/or repair efficiency of the redundant elements. Accordingly, it would be desirable to be able to implement a row redundancy scheme that reduces the impact on device area, and at the same time does not adversely affect access/address setup time or the repair efficiency of the elements.